Many modem computer architectures and information technology-related architectures comprise parallel data bus systems and other parallel bus structures, which are implemented to transport data, commands, status information and other pieces of information from one component to another. Examples do not only come from all over the field of computer technology, for instance from the field of inter-computer communication, such as via an external parallel port, but also from intra-computer communication, such as a communication between different components of a computer system, e.g., between a hard disk and a mass memory storage controller. Further examples can be derived from the field of intra-component communication such as the communication between individual memory devices and a buffer, or an intermediate communication device integrated along with the individual memory devices on a single memory module.
However, parallel bus structures are not only employed in the field of extra-chip communication as described above, but also inside individual chips and devices, which are then coupled via parallel bus structures as described above, to one another. Such bus structures are, for instance, used to transport data, commands, status signals and other pieces of information from an interface to a device-internal or chip-internal section, which is capable of storing, processing or otherwise manipulating the data, signals or other pieces of (encoded) information.
As an example, in DRAM devices (DRAM=Dynamic Random Access Memory) data busses are used to transport the data to be stored in the DRAM device from the input/output interfaces (IO) to the memory array of the DRAM device during a write operation (WRITE) and the data stored in the DRAM device from the memory array to the input/output interface during a read operation (READ).
With the ever-growing demand for larger memory capacities and the ever-growing demand for larger data processing capabilities, a key issue for bus structures becomes the speed at which data, signals and other pieces of information can be transported over the respective bus structures. Especially in the case of a parallel bus structure, for high-speed operations, it is necessary to reduce the skew between the different signal lines of the bus, which carry the different bits to be transported. Each of these different signal lines of the bus are very often connected to different, and hence, spatially distributed drivers or driver circuits.
Particularly, in the case of a read operation, in which the different pieces of information or bits which run on the different signal lines of the bus will be latched with only one signal indicating a read-finished state, the challenge of controlling and limiting the skew between the different signal lines of a bus becomes very important. Current solutions in the field of memory devices comprise no special method of reducing the skew on the busses which leads to a tracking of the signal indicating that the read operation is finished with the signals or bits being transmitted over the bus, as not being optimal.